Password protected modular computer method and device

ABSTRACT

A method and device for securing a removable Attached Computer Module (“ACM”)  10 . ACM  10  inserts into a Computer Module Bay (“CMB”)  40  within a peripheral console to form a functional computer such as a desktop computer or portable computer. The present ACM  10  includes a locking system, which includes hardware and software  600, 700 , to prevent accidental removal or theft of the ACM from the peripheral console. While ACM is in transit, further security is necessary against illegal or unauthorized use. If ACM contains confidential data, a high security method is needed to safeguard against theft.

CROSS REFERENCE TO RELATED APPLICATIONS

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 6,321,335. The reissue applications are U.S.application Ser. No. 10/963,825 (a parent reissue application), Ser. No.11/474,256 (which is a continuation reissue of the parent reissueapplication), Ser. No. 11/517,601 (which is a continuation reissue ofthe parent reissue application), Ser. No. 12/577,074 (which is acontinuation reissue of the parent reissue application), Ser. No.12/322,858 (which is a continuation reissue of U.S. application Ser. No.11/517,601), and Ser. No. 13/233,917 (the subject application, which isa continuation reissue of U.S. application Ser. No. 12/322,858).

This application is a continuation reissue filed Feb. 5, 2009, of U.S.application Ser. No. 12/322,858 now U.S. Pat. No. Re. 42,814, which is acontinuation reissue filed Sep. 6, 2006 of U.S. application Ser. No.11/517,601 now U.S. Pat. No. Re. 41,076, which is a continuation reissueof U.S. application Ser. No. 10/963,825 filed Oct. 12, 2004, now U.S.Pat. No. Re. 41,961 which is a reissue of U.S. Pat. No. 6,321,335, whichare incorporated herein by reference.

The following two commonly-owned copending applications, including thisone, are being filed concurrently and the other one is herebyincorporated by reference in their entirety for all purposes:

1. U.S. patent application Ser. No. 09/183,816, William W. Y. Chu,entitled, “Modular Computer Security Method and Device”. and

2. U.S. patent application Ser. No. 09/183,493, William W. Y. Chu,entitled, “Password Protected Modular Computer Method and Device”.

BACKGROUND OF THE INVENTION

The present invention relates to computing devices. More particularly,the present invention provides a method and device for securing apersonal computer or set-top box using password protection techniques.Merely by way of example, the present invention is applied to a modularcomputing environment for desk top computers, but it will be recognizedthat the invention has a much wider range of applicability. It can beapplied to a server as well as other portable or modular computingapplications.

Many desktop or personal computers, which are commonly termed PCs, havebeen around and used for over ten years. The PCs often come withstate-of-art microprocessors such as the Intel Pentium™ microprocessorchips. They also include a hard or fixed disk drive such as memory inthe giga-bit range. Additionally, the PCs often include a random accessmemory integrated circuit device such as a dynamic random access memorydevice, which is commonly termed DRAM. The DRAM devices now provide upto millions of memory cells (i.e., mega-bit) on a single slice ofsilicon. PCs also include a high resolution display such as cathode raytubes or CRTs. In most cases, the CRTs are at least 15 inches or 17inches or 20 inches in diameter. High resolution flat panel displays arealso used with PCs.

Many external or peripheral devices can be used with the PCs. Amongothers, these peripheral devices include mass storage devices such as aZip™ Drive product sold by Iomega Corporation of Utah. Other storagedevices include external hard drives, tape drives, and others.Additional devices include communication devices such as a modem, whichcan be used to link the PC to a wide area network of computers such asthe Internet. Furthermore, the PC can include output devices such as aprinter and other output means. Moreover, the PC can include specialaudio output devices such as speakers the like.

PCs also have easy to use keyboards, mouse input devices, and the like.The keyboard is generally configured similar to a typewriter format. Thekeyboard also has the length and width for easily inputting informationby way of keys to the computer. The mouse also has a sufficient size andshape to easily move a curser on the display from one location toanother location.

Other types of computing devices include portable computing devices suchas “laptop” computers and the like. Although somewhat successful, laptopcomputers have many limitations. These computing devices have poordisplay technology. In fact, these devices often have a smaller flatpanel display that has poor viewing characteristics. Additionally, thesedevices also have poor input devices such as smaller keyboards and thelike. Furthermore, these devices have limited common platforms totransfer information to and from these devices and other devices such asPCs.

Up to now, there has been little common ground between these platformsincluding the PCs and laptops in terms of upgrading, ease-of-use, cost,performance, and the like. Many differences between these platforms,probably somewhat intentional, has benefited computer manufacturers atthe cost of consumers. A drawback to having two separate computers isthat the user must often purchase both the desktop and laptop to have“total” computing power, where the desktop serves as a “regular”computer and the laptop serves as a “portable” computer. Purchasing bothcomputers is often costly and runs “thousands” of dollars. The user alsowastes a significant amount of time transferring software and databetween the two types of computers. For example, the user must oftencouple the portable computer to a local area network (i.e., LAN), to aserial port with a modem and then manually transfer over files and databetween the desktop and the portable computer. Alternatively, the useroften must use floppy disks to “zip” up files and programs that exceedthe storage capacity of conventional floppy disks, and transfer thefloppy disk data manually.

Another drawback with the current model of separate portable and desktopcomputer is that the user has to spend money to buy components andperipherals the are duplicated in at least one of these computers. Forexample, both the desktop and portable computers typically include harddisk drives, floppy drives, CD-ROMs, computer memory, host processors,graphics accelerators, and the like. Because program software andsupporting programs generally must be installed upon both hard drives inorder for the user to operate programs on the road and in the office,hard disk space is often wasted.

One approach to reduce some of these drawbacks has been the use of adocking station with a portable computer. Here, the user has theportable computer for “on the road” use and a docking station thathouses the portable computer for office use. The docking stationtypically includes a separate monitor, keyboard, mouse, and the like andis generally incompatible with other desktop PCs. The docking station isalso generally not compatible with portable computers of other vendors.Another drawback to this approach is that the portable computertypically has lower performance and functionality than a conventionaldesktop PC. For example, the processor of the portable is typically muchslower than processors in dedicated desktop computers, because of powerconsumption and heat dissipation concerns. As an example, it is notedthat at the time of drafting of the present application, sometop-of-the-line desktops include 400 MHz processors, whereastop-of-the-line notebook computers include 266 MHz processors.

Another drawback to the docking station approach is that the typicalcost of portable computers with docking stations can approach the costof having a separate portable computer and a separate desktop computer.Further, as noted above, because different vendors of portable computershave proprietary docking stations, computer users are held captive bytheir investments and must rely upon the particular computer vendor forfuture upgrades, support, and the like.

Thus what is needed are computer systems that provide reduced userinvestment in redundant computer components and provide a variable levelof performance based upon computer configuration.

SUMMARY OF THE INVENTION

According to the present invention, a technique including a method anddevice for securing a computer module using a password in a computersystem is provided. In an exemplary embodiment, the present inventionprovides a security system for an attached computer module (“ACM”). Inan embodiment, the ACM inserts into a Computer Module Bay (CMB) within aperipheral console to form a functional computer.

In a specific embodiment, the present invention provides a computermodule. The computer module has an enclosure that is insertable into aconsole. The module also has a central processing unit (i.e., integratedcircuit chip) in the enclosure. The module has a hard disk drive in theenclosure, where the hard disk drive is coupled to the centralprocessing unit. The module further has a programmable memory device inthe enclosure, where the programmable memory device can be configurableto store a password for preventing a possibility of unauthorized use ofthe hard disk drive and/or other module elements. The stored passwordcan be any suitable key strokes that a user can change from time totime. In a further embodiment, the present invention provides apermanent password or user identification code stored in flash memory,which also can be in the processing unit, or other integrated circuitelement. The permanent password or user identification code is designedto provide a permanent “finger print” on the attached computer module.

In a specific embodiment, the present invention provides a variety ofmethods. In one embodiment, the present invention provides a method foroperating a computer system such as a modular computer system andothers. The method includes inserting an attached computer module(“ACM”) into a bay of a modular computer system. The ACM has amicroprocessor unit (e.g., microcontroller, microprocessor) coupled to amass memory storage device (e.g., hard disk). The method also includesapplying power to the computer system and the ACM to execute a securityprogram, which is stored in the mass memory storage device. The methodalso includes prompting for a user password from a user on a display(e.g., flat panel, CRT). In a further embodiment, the present methodincludes a step of reading a permanent password or user identificationcode stored in flash memory, or other integrated circuit element. Thepermanent password or user identification code provides a permanentfinger print on the attached computer module. The present inventionincludes a variety of these methods that can be implemented in computercodes, for example, as well as hardware.

Numerous benefits are achieved using the present invention overpreviously existing techniques. The present invention providesmechanical and electrical security systems to prevent theft orunauthorized use of the computer system in a specific embodiment.Additionally, the present invention substantially prevents accidentalremoval of the ACM from the console. In some embodiments, the presentinvention prevents illegal or unauthorized use during transit. Thepresent invention is also implemented using conventional technologiesthat can be provided in the present computer system in an easy andefficient manner. Depending upon the embodiment, one or more of thesebenefits can be available. These and other advantages or benefits aredescribed throughout the present specification and are described moreparticularly below.

These and other embodiments of the present invention, as well as itsadvantages and features, are described in more detail in conjunctionwith the text below and attached FIGS.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram of a computer system according to anembodiment of the present invention;

FIG. 2 is a simplified diagram of a computer module according to anembodiment of the present invention;

FIG. 3 is a simplified side-view diagram of a computer module accordingto an embodiment of the present invention;

FIG. 4 is a simplified layout diagram of a security system for acomputer system according to an embodiment of the present invention;

FIG. 5 is a simplified block diagram of a security system for a computermodule according to an embodiment of the present invention; and

FIGS. 6 and 7 show simplified flow diagrams of security methodsaccording to embodiments of the present invention.

FIG. 8 is a block diagram of one embodiment of a computer system usingthe interface of the present invention.

FIG. 9 is a detailed block diagram of one embodiment of the hostinterface controller of the present invention.

FIG. 10 is a detailed block diagram of one embodiment of the PIC of thepresent invention.

FIG. 11 is a schematic diagram of the signal lines PCK, PD0 to PD3, andPCN.

FIG. 12 is a partial block diagram of a computer system in which thenorth and south bridges are integrated with the host and peripheralinterface controllers, respectively.

FIG. 13 shows an attached computer module with IntegratedCPU/NB/Graphics and Integrated HIC/SB.

FIG. 14 shows an attached computer module with single chip fullyintegrated: CPU, Cache, Core Logic, Graphics controller and Interfacecontroller.

FIG. 15 is a schematic diagram of another embodiment of the connectorsused to couple the HIC and PIC.

FIG. 16 is a diagram of an attached computer module with a “plug &display” port and direct power connection.

DESCRIPTION OF SPECIFIC EMBODIMENTS

I. System Hardware

FIG. 1 is a simplified diagram of a computer system 1 according to anembodiment of the present invention. This diagram is merely anillustration and should not limit the scope of the claims herein. One ofordinary skill in the art would recognize other variations,modifications, and alternatives. The computer system 1 includes anattached computer module (i.e., ACM) 10, a desktop console 20, amongother elements. The computer system is modular and has a variety ofcomponents that are removable. Some of these components (or modules) canbe used in different computers, workstations, computerized televisionsets, and portable or laptop units.

In the present embodiment, ACM 10 includes computer components, as willbe described below, including a central processing unit (“CPU”), IDEcontroller, hard disk drive, computer memory, and the like. The computermodule bay (i.e., CMB) 40 is an opening or slot in the desktop console.The CMB houses the ACM and provides communication to and from the ACM.The CMB also provides mechanical protection and support to ACM 10. TheCMB has a mechanical alignment mechanism for mating a portion of the ACMto the console. The CMB further has thermal heat dissipation sinks,electrical connection mechanisms, and the like. Some details of the ACMcan be found in co-pending patent application Nos. 09/149,882 and09/149,548 filed Sep. 8, 1998, commonly assigned, and herebyincorporated by reference for all purposes.

In a preferred embodiment, the present system has a security system,which includes a mechanical locking system, an electrical lockingsystem, and others. The mechanical locking system includes at least akey 11. The key 11 mates with key hole 13 in a lock, which provides amechanical latch 15 in a closed position. The mechanical latch, in theclosed position, mates and interlocks the ACM to the computer modulebay. The mechanical latch, which also has an open position, allows theACM to be removed from the computer module bay. Further details of themechanical locking system are shown in the Fig. below.

FIG. 2 is a simplified diagram of a computer module 10 according to anembodiment of the present invention. This diagram is merely anillustration and should not limit the scope of the claims herein. One ofordinary skill in the art would recognize other variations,modifications, and alternatives. Some of the reference numerals aresimilar to the previous Fig. for easy reading. The computer module 10includes key 11, which is insertable into keyhole 13 of the lock. Thelock has at least two position, including a latched or closed positionand an unlatched or open position. The latched position secures the ACMto the computer module bay. The unlatched or open position allows theACM to be inserted into or removed from the computer bay module. Asshown, the ACM also has a slot or opening 14, which allows the latch tomove into and out of the ACM. The ACM also has openings 17 in thebackside for an electrical and/or mechanical connection to the computermodule bay, which is connected to the console.

FIG. 3 is a simplified side-view diagram of a computer module accordingto an embodiment of the present invention. This diagram is merely anillustration and should not limit the scope of the claims herein. One ofordinary skill in the art would recognize other variations,modifications, and alternatives. Some of the reference numerals aresimilar to the previous FIG. for easy reading. As shown, the ACM moduleinserts into the computer module bay frame 19, which is in the console.A side 27 and a bottom 19 of ACM slide and fit firmly into the computermodule bay frame, which has at least a bottom portion 19 and backportion 26. A backside 23 of the ACM faces backside 26 of the frame. ACMalso has a front-side or face 25 that houses the lock and exposes thekeyhole 13 to a user. The key 11 is insertable from the face into thekeyhole.

As the ACM inserts into the frame, connector 17 couples and inserts intoconnector 21. Connector 17 electrically and mechanically interfaceelements of the ACM to the console through connector 21. Latch 14 shouldbe moved away from the bottom side 19 of the module bay frame beforeinserting the ACM into the frame. Once the ACM is inserted fully intothe frame, latch 15 is placed in a closed or lock position, where itkeeps the ACM firmly in place. That is, latch 15 biases against abackside portion 29 of the ACM enclosure to hold the ACM in place, wherethe connector 17 firmly engages, electrically and mechanically, withconnector 21. To remove the ACM, latch 15 is moved away or opened fromthe back side portion of the ACM enclosure. ACM is manually pulled outof the computer module bay frame, where connector 17 disengages withconnector 21. As shown, the key 11 is used to selectively move the latchin the open or locked position to secure the ACM into the frame module.

In most embodiments, the ACM includes an enclosure such as the onedescribed with the following components, which should not be limiting:

-   -   1) A CPU with cache memory;    -   2) Core logic device or means;    -   3) Main memory;    -   4) A single primary Hard Disk Drive (“HDD”) that has a security        program;    -   5) Flash memory with system BIOS and programmable user password;    -   6) Operating System, application software, data files on primary        HDD;    -   7) An interface device and connectors to peripheral console;    -   8) A software controllable mechanical lock, lock control means,        and other accessories.

The ACM connects to a peripheral console with power supply, a displaydevice, an input device, and other elements. Some details of theseelements with the present security system are described in more detailbelow.

FIG. 4 is a simplified layout diagram of a security system for acomputer system according to an embodiment of the present invention.This diagram is merely an illustration and should not limit the scope ofthe claims herein. One of ordinary skill in the art would recognizeother variations, modifications, and alternatives. The layout diagramillustrates the top-view of the module 10, where the backside components(e.g., Host Interface Controller) are depicted in dashed lines. Thelayout diagram has a first portion, which includes a central processingunit (“CPU”) module 400, and a second portion, which includes a harddrive module 420. A common printed circuit board 437 houses thesemodules and the like. Among other features, the ACM includes the centralprocessing unit module 400 with a cache memory 405, which is coupled toa north bridge unit 421, and a host interface controller 401. The hostinterface controller includes a lock control 403. As shown, the CPUmodule is disposed on a first portion of the attached computer module,and couples to connectors 17. Here, the CPU module is spatially locatednear connector 17.

The CPU module can use a suitable microprocessing unit, microcontroller,digital signal processor, and the like. In a specific embodiment, theCPU module uses, for example, a 400 MHz Pentium II microprocessor modulefrom Intel Corporation and like microprocessors from AMD Corporation,Cyrix Corporation (now National Semiconductor Corporation), and others.In other aspects, the microprocessor can be one such as the CompaqComputer Corporation Alpha Chip, Apple Computer Corporation PowerPC G3processor, and the like. Further, higher speed processors arecontemplated in other embodiments as technology increases in the future.

In the CPU module, host interface controller 401 is coupled toBIOS/flash memory 405. Additionally, the host interface controller iscoupled to a clock control logic, a configuration signal, and aperipheral bus. The present invention has a host interface controllerthat has lock control 403 to provide security features to the presentACM. Furthermore, the present invention uses a flash memory thatincludes codes to provide password protection or other electronicsecurity methods.

The second portion of the attached computer module has the hard drivemodule 420. Among other elements, the hard drive module includes northbridge 421, graphics accelerator 423, graphics memory 425, a powercontroller 427, an IDE controller 429, and other components. Adjacent toand in parallel alignment with the hard drive module is a personalcomputer interface (“PCI”) bus 431, 432. A power regulator 435 isdisposed near the PCI bus.

In a specific embodiment, north bridge unit 421 often couples to acomputer memory, to the graphics accelerator 423, to the IDE controller,and to the host interface controller via the PCI bus. Graphicsaccelerator 423 typically couples to a graphics memory 423, and otherelements. IDE controller 429 generally supports and provides timingsignals necessary for the IDE bus. In the present embodiment, the IDEcontroller is embodied as a 643U2 PCI-to IDE chip from CMD Technology,for example. Other types of buses than IDE are contemplated, for exampleEIDE, SCSI, 1394, and the like in alternative embodiments of the presentinvention.

The hard drive module or mass storage unit 420 typically includes acomputer operating system, application software program files, datafiles, and the like. In a specific embodiment, the computer operatingsystem may be the Windows98 operating system from Microsoft Corporationof Redmond Wash. Other operating systems, such as WindowsNT, MacOS8,Unix, and the like are also contemplated in alternative embodiments ofthe present invention. Further, some typical application softwareprograms can include Office98 by Microsoft Corporation, Corel PerfectSuite by Cord, and others. Hard disk module 420 includes a hard diskdrive. The hard disk drive, however, can also be replaced by removablehard disk drives, read/write CD ROMs, flash memory, floppy disk drives,and the like. A small form factor, for example 2.5″, is currentlycontemplated, however, other form factors, such as PC card, and the likeare also contemplated. Mass storage unit 240 may also support otherinterfaces than IDE. Among other features, the computer system includesan ACM with security protection. The ACM connects to the console, whichhas at least the following elements, which should not be limiting.

-   -   1) Connection to input devices, e.g. keyboard or mouse;    -   2) Connection to display devices, e.g. Monitor;    -   3) Add-on means, e.g. PCI add-on slots;    -   4) Removable storage media subsystem, e.g. Floppy drive, CDROM        drive;    -   5) Communication device, e.g. LAN or modem;    -   6) An interface device and connectors to ACM;    -   7) A computer module bay with a notch in the frame for ACM's        lock; and    -   8) Power supply and other accessories.

As noted, the computer module bay is an opening in a peripheral consolethat receives the ACM. The computer module bay provides mechanicalsupport and protection to ACM. The module bay also includes, among otherelements, a variety of thermal components for heat dissipation, a framethat provides connector alignment, and a lock engagement, which securesthe ACM to the console. The bay also has a printed circuit board tomount and mate the connector from the ACM to the console. The connectorprovides an interface between the ACM and other accessories.

FIG. 5 is a simplified block diagram 500 of a security system for acomputer module according to an embodiment of the present invention.This diagram is merely an illustration and should not limit the scope ofthe claims herein. One of ordinary skill in the art would recognizeother variations, modifications, and alternatives. The block diagram 500has a variety of features such as those noted above, as well as others.In the present diagram, different reference numerals are used to showthe operation of the present system.

The block diagram is an attached computer module 500. The module 500 hasa central processing unit, which communicates to a north bridge 541, byway of a CPU bus 527. The north bridge couples to main memory 523 viamemory bus 529. The main memory can be any suitable high speed memorydevice or devices such as dynamic random access memory (“DRAM”)integrated circuits and others. The DRAM includes at least 32 Meg. or 64Meg. and greater of memory, but can also be less depending upon theapplication. Alternatively, the main memory can be coupled directly withthe CPU in some embodiments. The north bridge also couples to a graphicssubsystem 515 via bus 542 543. The graphics subsystem can include agraphics accelerator, graphics memory, and other devices. Graphicssubsystem transmits a video signal 517 to an interface connector, whichcouples to a display, for example.

The attached computer module also includes a primary hard disk drivethat serves as a main memory unit for programs and the like. The harddisk can be any suitable drive that has at least 2 GB and greater. Asmerely an example, the hard disk is a Marathon 2250 (225 GB, 2 ½ inchdrive) product made by Seagate Corporation of Scotts Valley, but can beothers. The hard disk communicates to the north bridge by way of a harddisk drive controller and bus lines 502 and 531. The hard disk drivecontroller couples to the north bridge by way of the host PCI bus, whichconnects bus 537 to the north bridge. The hard disk includes computercodes that implement a security program according to the presentinvention. Details of the security program are provided below.

The attached computer module also has a flash memory device 505 with aBIOS. The flash memory device 505 also has codes for a user passwordthat can be stored in the device. The flash memory device generallypermits the storage of such password without a substantial use of power,even when disconnected. As merely an example, the flash memory devicehas at least 4 Meg. or greater of memory, or 16 Meg. or greater ofmemory. A host interface controller 507 communications communicates tothe north bridge via bus 535 and host PCI bus. The host interfacecontroller also has a lock control 509, which couples to a lock. Thelock is attached to the module and has a manual override to the lock onthe host interface controller in some embodiments. Host interfacecontroller 507 communicates to the console using bus 511, which couplesto connection connector 513.

In one aspect of the present invention the security system uses acombination of electrical and mechanical locking mechanisms. Referringto FIG. 5A, for example, the present system provides a lock statusmechanism in the host interface controller 509. The lock status of thelock is determined by checking a lock status bit 549, which is in thehost interface controller. The lock status bit is determined by a signal553, which is dependent upon the position of the lock. Here, theposition of the lock is closed in the ground 559 position, where thelatch couples to a ground plane in the module and/or system.Alternatively, the signal of the lock is at Vcc, for example, which isopen. Alternatively, the signal can be ground in the open position andVcc in the closed position, depending upon the application. Other signalschemes can also be used depending upon the application.

Once the status is determined, the host interface controller turns thelock via solenoid 557 in a lock on or lock off position, which isprovided through the control bit 551, for example. The control bit is ina register of the host interface controller in the present example. Byway of the signal schemes noted and the control bit, it is possible toplace the lock in the lock or unlock position in an electronic manner.Once the status of the lock is determined, the host interface controllercan either lock or unlock the latch on the module using a variety ofprompts, for example.

In a preferred embodiment, the present invention uses a passwordprotection scheme to electronically prevent unauthorized access to thecomputer module. The present password protection scheme uses acombination of software, which is a portion of the security program, anda user password, which can be stored in the flash memory device 505. Byway of the flash memory device, the password does not become erased byway of power failure or the lock. The password is substantially fixed incode, which cannot be easily erased. Should the user desire to changethe password, it can readily be changed by erasing the code, which isstored in flash memory and a new code (i.e., password) is written intothe flash memory. An example of a flash memory device can include aIntel Flash 28F800F3 series flash, which is available in 8 Mbit and 16Mbit designs. Other types of flash devices can also be used, however.Details of a password protection method are further explained below byway of the FIGS.

In a specific embodiment, the present invention also includes areal-time clock 510 in the ACM, but is not limited. The real-time clockcan be implemented using a reference oscillator 14.31818 MHz 508 thatcouples to a real-time clock circuit. The real-time clock circuit can bein the host interface controller. An energy source 506 such as a batterycan be used to keep the real-time clock circuit running even when theACM has been removed from the console. The real-time clock can be usedby a security program to perform a variety of functions. As merely anexample, these functions include: (1) fixed time period in which the ACMcan be used, e.g., ACM cannot be used at night; (2) programmed ACM to beused after certain date, e.g., high security procedure during owner'svacation or non use period; (3) other uses similar to a programmabletime lock. Further details of the present real-time clock are describedin the application listed under Ser. No. 09/183,816 noted above.

In still a further embodiment, the present invention also includes apermanent password or user identification code to identify the computermodule. In one embodiment, the permanent password or user code is storedin a flash memory device. Alternatively, the permanent password or usercode is stored in the central processing unit. The password or user codecan be placed in the device upon manufacture of such device.Alternatively, the password or user code can be placed in the device bya one time programming techniques using, for example, fuses or the like.The present password or user code provides a permanent “finger print” onthe device, which is generally hardware. The permanent finger print canbe used for identification purposes for allowing the user of thehardware to access the hardware itself, as well as other systems. Theseother systems include local and wide area networks. Alternatively, thesystems can also include one or more servers. The present password anduser identification can be quite important for electronic commerceapplications and the like. In one or more embodiments, the permanentpassword or user code can be combined with the password on flash memoryfor the security program, which is described below in more detail.

II. SECURITY DETECTION PROGRAMS

FIGS. 6 and 7 show simplified flow diagrams 600, 700 of security methodsaccording to embodiments of the present invention. These diagrams aremerely illustrations and should not limit the scope of the claimsherein. One of ordinary skill in the an would recognize othervariations, modifications, and alternatives. Referring to FIG. 6, whichconsiders an example for when the ACM is inserted into the computermodule bay in the console, ACM has already been inserted into theconsole and is firmly engaged in an electrical and mechanical manner. Acomputer system is powered up 601, which provides selected signals tothe microprocessor. The microprocessor oversees the operation of thecomputer system. The microprocessor searches the memory in, for example,the hard disk drive and execute a security program, step 603.

The security program runs through a sequence of steps before allowing auser to operate the present system with the ACM. Among other processes,the security program determines if an “Auto-lock” is ON. If so, thesecurity program goes via branch 606 to step 607. Alternatively, thesecurity program goes to step 609, which determines that the lock staysOFF and loops to step 627, which indicates that the ACM can be removedphysically from the console. In step 607, the security program turns aswitch or switching means that turns ON a lock, which can be electrical,mechanical, or a combination of electrical and mechanical.

In a specific embodiment, the security program turns OFF the power ofthe ACM and console. Here, the security program directs the OS to turnthe power OFF, step 613. In an embodiment where power failure occurs(step 611), a key is used to release a latch in the ACM on the lock 615,where the ACM can be removed, step 627. From step 613, the securityprogram determines if the ACM is to be removed, step 617. If not, thelock stays ON, step 619. Alternatively, the security detection programdetermines if the password (or other security code) matches with thedesignated password, step 621. If not, the lock stays ON, step 623.Alternatively, the security program releases the lock 625, which freesthe ACM. Next, the ACM can be removed, step 627.

In an alternative embodiment, the present invention provides a securitysystem for the ACM, which is outside the console or computer module bay.See, FIG. 7, for example. As shown, the security system is implementedto prevent illegal or unauthorized use (step 701) of the ACM, which hasnot been used in the console. Here, a key turns ON a lock (step 703).The lock moves a latch in the ACM to a specific spatial location thatphysically blocks the passage of the ACM into the computer module bay.Accordingly, the ACM cannot insert (step 705) into the computer modulebay.

In an alternative aspect, the key can be used to turn the lock OFF, step707. Here, the key moves the latch in a selected spatial location thatallows the ACM to be inserted into the computer bay module. In the OFFposition, the ACM inserts into the computer module bay, step 709. Oncethe ACM is in the bay, a user can begin operating the ACM through theconsole. In one embodiment, the computer console including the ACM goesthrough the sequence of steps in the above FIG., but is not limited.

In a specific embodiment, the present invention implements the sequencesabove using computer software. In other aspects, computer hardware canalso be used and is preferably in some applications. The computerhardware can include a mechanical lock, which is built into the ACM. Anexample of such mechanical lock is shown above, but can also be others.In other aspects, the lock can be controlled or accessed electronicallyby way of computer software. Here, the key can be used to as a manualoverride if the ACM or computer fails.

The lock is used to prevent theft and accidental removal inside CMB. Thecurrent invention locates the lock inside the ACM to allow a user tokeep a single key as ACM is moved from console to console at differentlocations. When ACM is in transit, the lock can be engaged using the keyso that the latch extends outside ACM's enclosure. The extended latchprevents ACM from being inserted into any CMB. This prevents any illegaluse of ACM by someone other than the user.

In one aspect of the invention, the user password is programmable. Thepassword can be programmable by way of the security program. Thepassword can be stored in a flash memory device within the ACM.Accordingly, the user of the ACM and the console would need to have theuser password in order to access the ACM. In the present aspect, thecombination of a security program and user password can provide the usera wide variety of security functions as follows:

-   -   1) Auto-lock capability when ACM is inserted into CMB;    -   2) Access privilege of program and data;    -   3) Password matching for ACM removal; and    -   4) Automatic HDD lock out if tempering is detected.

In still a further embodiment, the present invention also includes amethod for reading a permanent password or user identification code toidentify the computer module. In one embodiment, the permanent passwordor user code is stored in a flash memory device. Alternatively, thepermanent password or user code is stored in the central processingunit. The password or user code can be placed in the device uponmanufacture of such device. Alternatively, the password or user code canbe placed in the device by a one time programming techniques using, forexample, fuses or the like. The present password or user code provides apermanent “finger print” on the device, which is generally hardware. Thepermanent finger print can be used for identification purposes forallowing the user of the hardware to access the hardware itself, as wellas other systems. These other systems include local and wide areanetworks. Alternatively, the systems can also include one or moreservers. The present method allows a third party confirm the user by wayof the permanent password or user code. The present password and useridentification can be quite important for electronic commerceapplications and the like, which verify the user code or password. Inone or more embodiments, the permanent password or user code can becombined with the password on flash memory for the security program.

Two PCI or PCI-like buses are interfaced using a non-PCI or non-PCI-likechannel. PCI control signals are encoded into control bits, and thecontrol bits, rather than the control signals that they represent, andare transmitted on the interface channel. At the receiving end, thecontrol bits representing control signals are decoded back into PCIcontrol signals prior to being transmitted to the intended PCI bus.

The fact that control bits rather than control signals are transmittedon the interface channel allows using a smaller number of signalchannels and a correspondingly small number of conductive lines in theinterface channel than would otherwise be possible. This is because thecontrol bits can be more easily multiplexed at one end of the interfacechannel and recovered at the other end than control signals. Thisrelatively small number of signal channels used in the interface channelallows using low voltage differential signal (“LVDS”) channels for theinterface. An LVDS channel is more cable friendly, faster, consumes lesspower, and generates less noise than a PCI bus channel. Therefore, anLVDS channel is advantageously used for the hereto unused purpose ofinterfacing PCI or PCI-like buses. The relatively smaller number ofsignal channels in the interface also allows using connectors havingsmaller pins counts. As mentioned above an interface having a smallernumber of signal channels and, therefore, a smaller number of conductivelines is less bulky and less expensive than one having a larger numberof signal channels. Similarly, connectors having a smaller number ofpins are also less expensive and less bulky than connectors having alarger number of pins.

In a preferred embodiment, the interface channel has a plurality ofserial bit channels numbering fewer than the number of parallel buslines in each of the PCI buses and operates at a clock speed higher thanthe clock speed at which any of the bus lines operates. Morespecifically, the interface channel includes two sets of unidirectionalserial bit channels which transmit data in opposite directions such thatone set of bit channels transmits serial bits from the HIC to the PICwhile the other set transmits serial bits from the PIC to the HIC. Foreach cycle of the PCI clock, each bit channel of the interface channeltransmits a packet of serial bits.

FIG. 8 is a block diagram of one embodiment of a computer system 800using the interface of the present invention. Computer system 800includes an attached computer module (ACM) 805 and a peripheral console810. The ACM 805 and the peripheral console 810 are interfaced throughan exchange interface system (XIS) bus 815. The XIS bus 815 includespower bus 816, video bus 817 and peripheral bus (XPBus) 818, which isalso herein referred to as an interface channel. The power bus 816transmits power between ACM 805 and peripheral console 810. In apreferred embodiment power bus 816 transmits power at voltage levels of3.3 volts, 5 volts and 12 volts. Video bus 817 transmits video signalsbetween the ACM 805 and the peripheral console 810. In a preferredembodiment, the video bus 817 transmits analog Red Green Blue (RGB)video signals for color monitors, digital video signals (such as VideoElectronics Standards Association (VESA) Plug and Display's TransitionMinimized Differential signaling (TMDS) signals for flat paneldisplays), and television (TV) and/or super video (S-video) signals. TheXPBus 818 is coupled to host interface controller (HIC) 819 and toperipheral interface controller (PIC) 820, which is also sometimesreferred to as a bay interface controller.

In the embodiment shown in FIG. 8, HIC 819 is coupled to an integratedunit 821 that includes a CPU, a cache and a north bridge. In yet anotherembodiment, such as that shown in FIG. 12, the HIC and PIC areintegrated with the north and south bridges, respectively, such thatintegrated HIC and north bridge unit 1205 includes an HIC and a northbridge, while integrated PIC and south bridge unit 1210 includes a PICand a south bridge. FIG. 13 shows an attached computer module withintegrated CPU/NB/Graphics 1315 and Integrated HIC/SB 1320. FIG. 14shows an attached computer module with single chip 1425 fullyintegrated: CPU, Cache, Core Logic, Graphics controller and Interfacecontroller.

FIG. 9 is a detailed block diagram of one embodiment of the HIC of thepresent invention. As shown in FIG. 9, HIC 900 comprises bus controller910, translator 920, transmitter 930, receiver 940, a PLL 950, anaddress/data multiplexer (A/D MUX) 960, a read/write controller (RD/WRCntl) 970, a video serial to parallel converter 980 and a CPU control &general purpose input/output latch/driver (CPU CNTL & GPIO latch/driver)990.

HIC 900 is coupled to an optional flash memory BIOS configuration unit901. Flash memory unit 901 stores basic input output system (BIOS) andPCI configuration information and supplies the BIOS and PCIconfiguration information to A/D MUX 960 and RD/WR Control 970, whichcontrol the programming, read, and write of flash memory unit 901.

Bus controller 910 is coupled to the host PCI bus, which is alsoreferred to herein as the primary PCI bus, and manages PCI bustransactions on the host PCI bus. Bus controller 910 includes a slave(target) unit 911 and a master unit 916. Both slave unit 911 and masterunit 916 each include two first in first out (FIFO) buffers, which arepreferably asynchronous with respect to each other since the input andoutput of the two FIFOs in the master unit 916 as well as the two FIFOsin the slave unit 911 are clocked by different clocks, namely the PCIclock and the PCK. Additionally, slave unit 911 includes encoder 922 anddecoder 923, while master unit 916 includes encoder 927 and decoder 928.The FIFOs 912, 913, 917 and 918 manage data transfers between the hostPCI bus and the XPBus, which in the embodiment shown in FIG. 9 operateat 33 MHz and 66 MHz, respectively. PCI address/data (AD) from the hostPCI bus is entered into FIFOs 912 and 917 before they are encoded byencoders 922 and 927. Encoders 922 and 927 format the PCI address/databits to a form more suitable for parallel to serial conversion prior totransmittal on the XPBus. Similarly, address and data information fromthe receivers is decoded by decoders 923 and 928 to a form more suitablefor transmission on the host PCI bus. Thereafter the decoded data andaddress information is passed through FIFOs 913 and 918 prior to beingtransferred to the host PCI bus. FIFOs 912, 913, 917 and 918 allow buscontroller 910 to handle posted and delayed PCI transactions and toprovide deep buffering to store PCI transactions.

Bus controller 910 also comprises slave read/write control (RD/WR Cntl)914 and master read/write control (RD/WR Cntl) 915. RD/WR controls 914and 915 are involved in the transfer of PCI control signals between buscontroller 910 and the host PCI bus.

Bus controller 910 is coupled to translator 920. Translator 920comprises encoders 922 and 927, decoders 923 and 928, control decoder &separate data path unit 924 and control encoder & merge data path unit925. As discussed above encoders 922 and 927 are part of slave data unit911 and master data unit 916, respectively, receive PCI address and datainformation from FIFOs 912 and 917, respectively, and encode the PCIaddress and data information into a form more suitable for parallel toserial conversion prior to transmittal on the XPBus. Similarly, decoders923 and 928 are part of slave data unit 911 and master data unit 916,respectively, and format address and data information from receiver 940into a form more suitable for transmission on the host PCI bus. Controlencoder & merge data path unit 925 receives PCI control signals from theslave RD/WR control 914 and master RD/WR control 915. Additionally,control encoder & merge data path unit 925 receives control signals fromCPU CNTL & GPIO latch/driver 990, which is coupled to the CPU and northbridge (not shown in FIG. 9). Control encoder & merge data path unit 925encodes PCI control signals as well as CPU control signals and northbridge signals into control bits, merges these encoded control bits andtransmits the merged control bits to transmitter 930, which thentransmits the control bits on the data lines PD0 to PD3 and control linePCN of the XPBus. Examples of control signals include PCI controlsignals and CPU control signals. A specific example of a control signalis FRAME# used in PCI buses. A control bit, on the other hand, is a databit that represents a control signal. Control decoder & separate datapath unit 924 receives control bits from receiver 940 which receivescontrol bits on data lines PDR0 to PDR3 and control line PCNR of theXPBus. Control decoder & separate data path unit 924 separates thecontrol bits it receives from receiver 940 into PCI control signals, CPUcontrol signals and north bridge signals, and decodes the control bitsinto PCI control signals, CPU control signals, and north bridge signals,all of which meet the relevant timing constraints.

Transmitter 930 receives multiplexed parallel address/data (A/D) bitsand control bits from translator 920 on the AD[31::0] out and the CNTLout lines, respectively. Transmitter 930 also receives a clock signalfrom PLL 950. PLL 950 takes a reference input clock and generates PCKthat drives the XPBus. PCK is asynchronous with the PCI clock signal andoperates at 66 MHz, twice the speed of the PCI clock of 33 MHz. Thehigher speed is intended to accommodate at least some possible increasesin the operating speed of future PCI buses. As a result of the higherspeed, the XPBus may be used to interface two PCI or PCI-like busesoperating at 66 MHz rather than 33 MHz or having 64 rather than 32multiplexed address/data lines.

The multiplexed parallel A/D bits and some control bits input totransmitter 930 are serialized by parallel to serial converters 932 oftransmitter 930 into 10 bit packets. These bit packets are then outputon data lines PD0 to PD3 of the XPBus. Other control bits are serializedby parallel to serial converter 933 into 10 bit packets and send out oncontrol line PCN of the XPBus.

FIG. 10 is a detailed block diagram of one embodiment of the PIC of thepresent invention. PIC 1000 is nearly identical to HIC 900 in itsfunction, except that HIC 900 interfaces the host PCI bus to the XPBuswhile PIC 1000 interfaces the secondary PCI bus to the XPBus. Similarly,the components in PIC 1000 serve the same function as theircorresponding components in HIC 900. Reference numbers for components inPIC 1000 have been selected such that a component in PIC 1000 and itscorresponding component in HIC 900 have reference numbers that have thesame two least significant digits. Thus for example, the bus controllerin PIC 1000 is referenced as bus controller 1010 while the buscontroller in HIC 900 is referenced as bus controller 910. As many ofthe elements in PIC 1000 serve the same functions as those served bytheir corresponding elements in HIC 900 and as the functions of thecorresponding elements in HIC 900 have been described in detail above,the function of elements of PIC 1000 having corresponding elements inHIC 900 will not be further described herein. Reference may be made tothe above description of FIG. 9 for an understanding of the functions ofthe elements of PIC 1000 having corresponding elements in HIC 900.

As suggested above, there are also differences between HIC 900 and PIC1000. Some of the differences between HIC 900 and PIC 1000 include thefollowing. First, receiver 1040 in PIC 1000, unlike receiver 940 in HIC900, does not contain a synchronization unit. As mentioned above, thesynchronization unit in HIC 900 synchronizes the PCKR clock to the PCKclock locally generated by PLL 950. PIC 1000 does not locally generate aPCK clock and, therefore, it does not have a locally generated PCK clockwith which to synchronize the PCK clock signal that it receives from HIC900. Another difference between PIC 1000 and HIC 900 is the fact thatPIC 1000 contains a video parallel to serial converter 1089 whereas HIC900 contains a video serial to parallel converter 980. Video parallel toserial converter 1089 receives 16 bit parallel video capture data andvideo control signals on the Video Port Data [0::15] and Video PortControl lines, respectively, from the video capture circuit (not shownin FIG. 10) and converts them to a serial video data stream that istransmitted on the VPD line to the HIC. The video capture circuit may beany type of video capture circuit that outputs a 16 bit parallel videocapture data and video control signals. Another difference lies in thefact that PIC 1000, unlike HIC 900, contains a clock doubler 1082 todouble the video clock rate of the video clock signal that it receives.The doubled video clock rate is fed into video parallel to serialconverter 1082 through buffer 1083 and is sent to serial to parallelconverter 980 through buffer 1084. Additionally, reset control unit 1035in PIC 1000 receives a reset signal from the CPU CNTL & GPIOlatch/driver unit 1090 and transmits the reset signal on the RESET# lineto the HIC 900 whereas reset control unit 945 of HIC 900 receives thereset signal and forwards it to its CPU CNTL & GPIO latch/driver unit990 because, in the above embodiment, the reset signal RESET# isunidirectionally sent from the PIC 1000 to the HIC 900.

Like HIC 900, PIC 1000 handles the PCI bus control signals and controlbits from the XPBus representing PCI control signals in the followingways:

1. PIC 1000 buffers clocked control signals from the secondary PCI bus,encodes them and sends the encoded control bits to the XPBus;

2. PIC 1000 manages the signal locally; and

3. PIC 1000 receives control bits from XPBus, translates them into PCIcontrol signals and sends the PCI control signals to the secondary PCIbus.

PIC 1000 also supports a reference arbiter on the secondary PCI Bus tomanage the PCI signals REQ# and GNT#.

FIG. 11 is a schematic diagram of lines PCK, PD0 to PD3, and PCN. Theselines are unidirectional LVDS lines for transmitting clock signals andbits from the HIC to the PIC. The bits on the PD0 to PD3 and the PCNlines are sent synchronously within every clock cycle of the PCK.Another set of lines, namely PCKR, PDR0 to PDR3, and PCNR, are used totransmit clock signals and bits from the PIC to HIC. The lines used fortransmitting information from the PIC to the HIC have the same structureas those shown in FIG. 11, except that they transmit data in a directionopposite to that in which the lines shown in FIG. 11 transmit data. Inother words they transmit information from the PIC to the HIC. The bitson the PDR0 to PDR3 and the PCNR lines are sent synchronously withinevery clock cycle of the PCKR. Some of the examples of controlinformation that may be sent in the reverse direction, i.e., on PCNRline, include a request to switch data bus direction because of apending operation (such as read data available), a control signal changein the target requiring communication in the reverse direction, targetbusy, and transmission error detected.

The XPBus which includes lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3,and PCNR, has two sets of unidirectional lines transmitting clocksignals and bits in opposite directions. The first set of unidirectionallines includes PCK, PD0 to PD3, and PCN. The second set ofunidirectional lines includes PCKR, PDR0 to PDR3, and PCNR. Each ofthese unidirectional set of lines is a point-to-point bus with a fixedtransmitter and receiver, or in other words a fixed master and slavebus. For the first set of unidirectional lines, the HIC is a fixedtransmitter/master whereas the PIC is a fixed receiver/slave. For thesecond set of unidirectional lines, the PIC is a fixedtransmitter/master whereas the HIC is a fixed receiver/slave. The LVDSlines of XPBus, a cable friendly and remote system I/O bus, transmitfixed length data packets within a clock cycle.

The XPBus lines, PD0 to PD3, PCN, PDR0 to PDR3 and PCNR, and the videodata and clock lines, VPD and VPCK, are not limited to being LVDS lines,as they may be other forms of bit based lines. For example, in anotherembodiment, the XPBus lines may be IEEE 1394 lines.

It is to be noted that although each of the lines PCK, PD0 to PD3, PCN,PCKR, PDR0 to PDR3, PCNR, VPCK, and VPD is referred to as a line, in thesingular rather than plural, each such line may contain more than onephysical line. For example, in the embodiment shown in FIG. 11, each oflines PCK, PD0 to PD3 and PCN includes two physical lines between eachdriver and its corresponding receiver. The term line, when not directlypreceded by the terms physical or conductive, is herein usedinterchangeably with a signal or bit channel of one or more physicallines for transmitting a signal. In the case of non-differential signallines, generally one physical line is used to transmit one signal.However, in the case of differential signal lines, a pair of physicallines is used to transmit one signal. For example, a pair of physicallines together transmit a signal in a bit line or bit channel in an LVDSor IEEE 1394 interface.

A bit based line (i.e., a bit line) is a line for transmitting serialbits. Bit based lines typically transmit bit packets and use a serialdata packet protocol. Examples of bit lines include an LVDS line, anIEEE 1394 line, and a Universal Serial Bus (USB) line.

In another embodiment, such as that shown in FIG. 15, the connectors onthe HIC and PIC do not directly engage with one another. In theembodiment shown in FIG. 15, an extension cord 1580 having cable 1583and connectors 1581 and 1582 disposed at the ends of cable 1583, is usedto couple the connectors 1505 and 1555 on the HIC 1500 and PIC 1550,respectively. FIG. 16 is a diagram of an attached computer module 1600with a “plug & display” port and direct power connection.

The interfaces of the present invention comprising an HIC, a PIC and thelink between the HIC and PIC, either with or without an extension cordsuch as extension cord 1580 in FIG. 15, may be used to interface an ACMand a peripheral console. Moreover, the embodiment of the interface ofthe present invention having an extension cord, such as that disclosedin FIG. 15, may be used to interface two computer systems. Therefore,the interface of the present invention has broader application than thatof interfacing an ACM and a peripheral console.

In one embodiment, the connectors may be limited to pins fortransmitting PCI related signals. In such an embodiment, the cable wouldconsist of conductive lines on the XPBus. In another embodiment,however, the connectors may include pins for transmitting video and/orpower related signals in addition to the PCI related signals, in whichcase, the cable would have conductive lines for the video bus and/orpower bus.

The above embodiments are described generally in terms of hardware andsoftware. It will be recognized, however, that the functionality of thehardware can be further combined or even separated. The functionality ofthe software can also be further combined or even separated. Hardwarecan be replaced, at times, with software. Software can be replaced, attimes, with hardware. Accordingly, the present embodiments should not beconstrued as limiting the scope of the claims here. One of ordinaryskill in the art would recognize other variations, modifications, andalternatives.

While the above is a full description of the specific embodiments,various modifications, alternative constructions and equivalents may beused. Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A computer module, said module comprising: anenclosure, said enclosure comprising a first connector configured tocouple to a second connector through a cable, said second connectorbeing insertable into a console; a central processing unit in saidenclosure, said central processing unit comprising a microprocessorbased integrated circuit chip and an interface controller integrated insaid chip, said interface controller being configured to transmit andreceive serial bits of Peripheral Component Interconnect (“PCI”) bustransaction, said serial bits of PCI bus transaction comprising PCIaddress and data bits; a low voltage differential signal (“LVDS”)channel in said enclosure, said LVDS channel comprising a firstunidirectional, differential signal pair to convey data in a firstdirection and a second unidirectional, differential signal pair toconvey data in a second, opposite direction, said LVDS channel directlyextending from said interface controller to convey said serial bits ofPCI bus transaction; a hard disk drive in said enclosure, said hard diskdrive being coupled to said central processing unit; and a programmablememory device in said enclosure, said programmable memory device beingconfigurable to store a password for preventing a possibility ofunauthorized use of said hard disk drive.
 2. The computer module ofclaim 1 further comprising a host interface controller for providing astatus of a locking device in said enclosure.
 3. The computer module ofclaim 1 further comprising a mechanical locking device that is coupledto said programmable memory device.
 4. The computer module of claim 1further comprising a host interface controller coupled to a mechanicallocking device, said host interface controller being coupled to saidprogrammable memory device.
 5. The computer module of claim 1 whereinsaid programmable memory device comprises a flash memory device.
 6. Thecomputer module of claim 1 wherein said programmable memory devicecomprises a flash memory device having at least 8 Mbits of cells andgreater.
 7. The computer module of claim 1 further comprising a securityprogram in a main memory.
 8. The computer module of claim 7 wherein saidsecurity program comprises a code for storing a password on saidprogrammable memory device.
 9. The computer module of claim 8 whereinsaid security program comprises a code for checking a time from saidreal-time clock circuit.
 10. The computer module of claim 1 furthercomprising a host interface controller coupled to a solenoid that drivesa mechanical lock in a first position to a second position.
 11. Thecomputer module of claim 10 wherein said solenoid also drives saidmechanical lock from said second position to said first position. 12.The computer module of claim 1 further comprising a real-time clockcircuit coupled to said central processing unit.
 13. The computer moduleof claim 12 further comprising a battery coupled to a host interfacecontroller that includes said real-time clock.
 14. A method foroperating a computer system, said method comprising: inserting anattached computer module (“ACM”) into a bay of a console of a modularcomputer system, said ACM comprising a low voltage differential signal(“LVDS”) channel comprising at least two unidirectional serial bitchannels to convey data in opposite directions; and a microprocessorunit coupled to a mass memory storage device, said microprocessor unitcomprising an interface controller coupled to said LVDS channel tocommunicate Peripheral Component Interconnect (“PCI”) bus transaction inserial form over said LVDS channel; applying power to said computersystem and said ACM to execute a security program, said security programbeing stored in said mass memory storage device; and prompting for auser password from a user on a display.
 15. The method of claim 14wherein said ACM comprises an enclosure that houses said microprocessorunit and said mass memory storage device.
 16. The method of claim 14further comprising providing a user password to said security program.17. The method of claim 14 further comprising wherein said mass memorystorage device comprises a flash memory device for storing a desiredpassword for said ACM.
 18. The method of claim 17 wherein said flashmemory device maintains said desired password when power is removed fromsaid ACM.
 19. The method of claim 18 wherein said flash memory device iscoupled to a host interface controller that is coupled to saidmicroprocessor based unit.
 20. The method of claim 14 wherein said massmemory storage device comprises a code directed to comparing said userpassword with a desired password.
 21. The method of claim 14 furthercomprising identifying a permanent password or user code on saidattached computer module.
 22. The method of claim 21 wherein saidpermanent password or user code is stored in said microprocessor unit.23. The method of claim 21 wherein said permanent password or user codeis stored in a flash memory device coupled to said microprocessor unit.24. The computer module of claim 1 wherein said central processing unitcomprises a graphics controller integrated in said chip.
 25. Thecomputer module of claim 24 wherein said console comprises a display,and said graphics controller is configured to couple to said displayupon insertion of said second connector into said console.
 26. Thecomputer module of claim 1 wherein said interface controller isconfigured to output encoded address and data bits of PCI bustransaction in serial form that are conveyed over said LVDS channel. 27.The computer module of claim 1 wherein said LVDS channel corresponds toa first LVDS channel, said console comprises a second LVDS channel, andsaid first LVDS channel is configured to couple to said second LVDSchannel upon insertion of said second connector into said console. 28.The method of claim 14 wherein said interface controller is configuredto output an encoded serial bit stream of PCI address and datainformation, said LVDS channel directly extends from said interfacecontroller, and further comprising conveying said encoded serial bitstream over said LVDS channel.
 29. The method of claim 14 wherein saidmicroprocessor unit comprises a graphics controller integrated with saidmicroprocessor unit in a single chip, and further comprising couplingsaid graphics controller to said display upon insertion of said ACM. 30.A computer module, said module comprising: an enclosure, said enclosurecomprising a first connector configured to couple to a second connectorthrough a cable, said second connector being insertable into a console,said console comprising a Universal Serial Bus; a central processingunit in said enclosure, said central processing unit comprising amicroprocessor based integrated circuit chip and an interface controllerintegrated in said chip; a low voltage differential signal (“LVDS”)channel directly extending from said interface controller, said LVDSchannel comprising two sets of unidirectional serial bit channels toconvey data in opposite directions; a hard disk drive in said enclosure,said hard disk drive being coupled to said central processing unit; anda programmable memory device in said enclosure, said programmable memorydevice being configurable to store a password for preventing apossibility of unauthorized use of said hard disk drive.
 31. Thecomputer module of claim 30 wherein said interface controller isconfigured to output an encoded serial bit stream that is conveyed oversaid LVDS channel.
 32. The computer module of claim 31 wherein saidencoded serial bit stream is conveyed over said LVDS channel as 10-bitpackets.
 33. The computer module of claim 31 wherein said encoded serialbit stream comprises encoded address and data bits of PeripheralComponent Interconnect (“PCI”) bus transaction.
 34. The computer moduleof claim 31 wherein said encoded serial bit stream comprises informationof Universal Serial Bus protocol.
 35. The computer module of claim 34wherein said LVDS channel is configured to couple to said UniversalSerial Bus upon insertion of said second connector into said console.36. The computer module of claim 31 further comprising a main memory insaid enclosure, said main memory being directly coupled to said centralprocessing unit.
 37. A computer module, said module comprising: anenclosure, said enclosure comprising a first connector configured tocouple to a second connector through a cable, said second connectorbeing insertable into a console, said console comprising a mass storagedevice and a first channel comprising two low voltage differentialsignal (“LVDS”), unidirectional serial bit channels to convey data inopposite directions; a central processing unit in said enclosure, saidcentral processing unit comprising a microprocessor based integratedcircuit chip and an interface controller integrated in said chip, saidinterface controller being configured to communicate address and data ofPeripheral Component Interconnect (“PCI”) bus transaction in serialform; a second channel directly coupled to said interface controller,said second channel comprising two LVDS, unidirectional, multiple serialbit channels to convey data in opposite directions; a hard disk drive insaid enclosure, said hard disk drive being coupled to said centralprocessing unit; and a programmable memory device in said enclosure,said programmable memory device being configurable to store a passwordfor preventing a possibility of unauthorized use of said hard diskdrive.
 38. The computer module of claim 37 wherein, upon insertion ofsaid second connector into said console, said first channel isconfigured to couple to said second channel to communicate said addressand data of PCI bus transaction.
 39. The computer module of claim 37wherein, upon insertion of said second connector into said console, saidcentral processing unit is configured to couple to said mass storagedevice through said first channel and said second channel.
 40. Thecomputer module of claim 37 wherein said interface controller isconfigured to output said address and data of PCI bus transaction as10-bit packets that are conveyed over said second channel.
 41. Thecomputer module of claim 37 further comprising a main memory in saidenclosure, said main memory being directly coupled to said centralprocessing unit.
 42. A computer module, said module comprising: anenclosure, said enclosure comprising a first connector configured tocouple to a second connector through a cable, said second connectorbeing insertable into a console, said console comprising a mass storagedevice and a first channel comprising two low voltage differentialsignal (“LVDS”), unidirectional serial bit channels to convey data inopposite directions; a central processing unit in said enclosure, saidcentral processing unit comprising a microprocessor based integratedcircuit chip; a second channel in said enclosure, said second channelcomprising two LVDS, unidirectional, multiple serial bit channels toconvey data in opposite directions; a peripheral bridge to communicateaddress and data of Peripheral Component Interconnect (“PCI”) bustransaction in serial form over said second channel, said peripheralbridge coupled to said central processing unit without any interveningPCI bus; a hard disk drive in said enclosure, said hard disk drive beingcoupled to said central processing unit; and a programmable memorydevice in said enclosure, said programmable memory device beingconfigurable to store a password for preventing a possibility ofunauthorized use of said hard disk drive.
 43. The computer module ofclaim 42 wherein, upon insertion of said second connector into saidconsole, said first channel is configured to couple to said secondchannel to communicate said address and data of PCI bus transaction. 44.The computer module of claim 42 wherein, upon insertion of said secondconnector into said console, said central processing unit is configuredto couple to said mass storage device through said second channel. 45.The computer module of claim 42 wherein said second channel directlyextends from said peripheral bridge.
 46. The computer module of claim 45wherein said peripheral bridge is configured to output said address anddata of PCI bus transaction as 10-bit packets that are conveyed oversaid second channel.
 47. A computer module, said module comprising: anenclosure, said enclosure comprising a first connector configured tocouple to a second connector through a cable, said second connectorbeing insertable into a console; a central processing unit in saidenclosure, said central processing unit comprising a microprocessorbased integrated circuit chip and an interface controller integrated insaid chip, said interface controller being configured to transmit andreceive serial bits of Peripheral Component Interconnect (“PCI”) bustransaction as 10-bit packets, said serial bits of PCI bus transactioncomprising encoded PCI address and data bits; a low voltage differentialsignal (“LVDS”) channel in said enclosure, said LVDS channel comprisinga first unidirectional, differential signal pair to convey data in afirst direction and a second unidirectional, differential signal pair toconvey data in a second, opposite direction, said LVDS channel directlyextending from said interface controller to convey said serial bits ofPCI bus transaction; a hard disk drive in said enclosure, said hard diskdrive being coupled to said central processing unit; and a programmablememory device in said enclosure, said programmable memory device beingconfigurable to store a password for preventing a possibility ofunauthorized use of said hard disk drive.
 48. The computer module ofclaim 47 wherein said console comprises a mass storage device, and, uponinsertion of said second connector into said console, said centralprocessing unit is configured to communicate with said mass storagedevice through said LVDS channel.
 49. The computer module of claim 47wherein said LVDS channel extends through said first connector to conveysaid serial bits of PCI bus transaction between said computer module andsaid console.
 50. The computer module of claim 47 wherein said consolecomprises a display, and said first connector is configured to conveyvideo signals between said computer module and said console.
 51. Thecomputer module of claim 50 wherein said central processing unitcomprises a graphics controller integrated in said chip.
 52. Thecomputer module of claim 51 wherein said graphics controller isconfigured to communicate with said display through said firstconnector.
 53. A method for operating a computer system, said methodcomprising: inserting an attached computer module (“ACM”) into a bay ofa console of a modular computer system, said console comprising an inputdevice, said ACM comprising a microprocessor unit coupled to a massmemory storage device, said microprocessor unit comprising an interfacecontroller to communicate Peripheral Component Interconnect (“PCI”) bustransaction in serial form; and a low voltage differential signal(“LVDS”) channel comprising at least two unidirectional serial bitchannels to convey data in opposite directions, said LVDS channeldirectly extending from said interface controller to convey said PCI bustransaction in serial form; conveying data packets of Universal SerialBus protocol between said ACM and said console; applying power to saidcomputer system and said ACM to execute a security program, saidsecurity program being stored in said mass memory storage device; andprompting for a user password from a user on a display.
 54. The methodof claim 53 wherein said interface controller is configured to output aserial bit stream of PCI address and data information, and furthercomprising conveying said serial bit stream over said LVDS channel. 55.The method of claim 53 wherein said mass memory storage device comprisesa flash memory device.
 56. The method of claim 53 wherein conveying saiddata packets of Universal Serial Bus protocol comprises conveying saiddata packets over serial bit lines.
 57. The method of claim 53 whereinconveying said data packets of Universal Serial Bus protocol comprisesconveying said data packets between said ACM and said input device. 58.The method of claim 53 wherein said microprocessor unit comprises agraphics controller integrated with said microprocessor unit in a singlechip, and further comprising coupling said graphics controller to saiddisplay upon insertion of said ACM.
 59. The computer module of claim lwherein said LVDS channel extends through said first connector to conveysaid serial bits of PCI bus transaction between said computer module andsaid console.